As semiconductor process technology nodes advance to smaller dimensions and lower supply voltages, yields of products depend on a lower limit of a supply voltage value, such as VDDmin. A VDDmin value is designed to work for both writing data to and reading data from a memory cell. As VDDmin value is lowered, a lower yield results, however.
In an existing approach related to static random access memory (SRAM), an NMOS passgate transistor tends to pull data stored in a memory cell towards a reference voltage VSS while a pull-up PMOS transistor in the memory cell tends to pull the same data towards a supply voltage VDD. In order to provide a sufficient margin for writing data to a node of the memory cell, a size of the NMOS passgate transistor is designed to be about two to three times a size of the PMOS pull-up transistor. An increase in a size of the NMOS passgate transistor results in a bigger size of the memory cell and additional leakage current.
Like reference symbols in the various drawings indicate like elements.